Formation of metal wiring interconnects in integrated circuits (ICs) can be achieved using a damascene or dual damascene process. Typically, trenches or holes are etched into dielectric material, such as silicon dioxide, located on a substrate. The holes or trenches may be lined with one or more adhesion and/or diffusion barrier layers. Then a thin layer of metal may be deposited in the holes or trenches that can act as a seed layer for electroplated metal. Thereafter, the holes or trenches may be filled with electroplated metal.
Typically, the seed metal is copper. However, other metals such as ruthenium, palladium, iridium, rhodium, osmium, cobalt, nickel, gold, silver, and aluminum, or alloys of these metals, may also be used.
To achieve higher performance ICs, many of the features of the ICs are being fabricated with smaller feature sizes and higher densities of components. In some damascene processing, for example, copper seed layers on 2×-nm node features may be as thin as or thinner than 50 Å. Technical challenges arise with smaller feature sizes in producing metal seed layers and metal interconnects substantially free of voids or defects.